To maximize the energy harvested from solar panels, cascaded multilevel inverter topology has been considered in photovoltaic (PV) applications for decades. The cascaded multilevel inverter topology features separate DC (direct current) inputs, making possible the string, or even panel level, maximum power point tracking. The energy harvested from the solar panels can be maximized in case of mismatch in the PV panels due to panel aging, shading effect or accumulation of dust in the panel surface. The cascaded structure can also generate high-quality output waveforms with each semiconductor of the cascaded inverter switching at lower frequency. Moreover, the number of cascaded modules can be extended to allow a transformerless connection to the grid. Consequently, the cascaded multilevel inverter topology can achieve greater DC/AC conversion efficiency. Additionally, compared with conventional central/string inverters, less expensive power semiconductors, having a lower voltage rating, can be utilized.
However, the transformerless structure of the cascaded inverters results in undesirable galvanic connections between the grid and the PV panels interfaced with separate cascaded inverters. Due to the parasitic capacitance between the PV panels and earth ground, circulating leakage current can flow through the panels and grid ground, leading to an undesirable increase of the output harmonic content, higher losses, safety concerns and electromagnetic interference problems.
In a PV cascaded multilevel inverter topology, two types of leakage current loops may exist. With reference to FIG. 1, in a PV cascaded multiple inverter 100, a first leakage current loop 105 is formed by the parasitic capacitance 110a, 110b, 110c, inverter-bridge 115a, 115b, 115c and grid ground 120. The second leakage current loop 125 is formed between the individual inverter bridges 115a, 115b, 115c of the cascaded multilevel inverter. The second leakage current loop 125 between the inverter bridges 115a, 115b, 115c is a capacitive coupling path exhibiting negligible inductance. The high-frequency pulse-width modulation (PWM) voltage of the cascaded inverter results in pulsewise leakage current in the second leakage current loop. In comparison to single transformerless inverters, the second leakage current loop is a unique leakage current loop in the cascaded multiple inverter topology. In addition, the second leakage current loop is present regardless of whether or not there is a transformer at the cascaded inverter output.
Leakage current suppression techniques for conventional single transformerless inverters have been well reported. However, there has been limited research regarding the leakage current issues in PV cascaded multilevel inverters. The leakage current issue present a challenge for the design of a reliable PV system based on a cascaded multilevel inverter. There exists a need in the art for a system and method that can produce a reliable PV system based on a cascaded multilevel inverter.
However, in view of the art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the field of this invention how the shortcomings of the prior art could be overcome.